The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a bipolar integrated circuit with I.sup.2 L elements.
An I.sup.2 L (Integrated Injection Logic) is a logic element which has a composite structure involving a vertical transistor (e.g., an npn transistor) of inverted structure and a lateral transistor (e.g., pnp transistor) of complementary structure to that of the vertical transistor. In an I.sup.2 L of the structure as described above, the lateral transistor serves as an injector for injecting charge to the base of the vertical transistor of the inverted structure, and the vertical transistor of the inverted structure serves as an inverter. For this reason, an I.sup.2 L is receiving a lot of attention as a logic element which has a small logic amplitude and which is capable of operating at high speed and with low power consumption. Since the element isolation between the vertical and lateral transistors is unnecessary, an I.sup.2 L can achieve a high integration and is suitable for large scale integration. Furthermore, since an I.sup.2 L involves bipolar process technique, other bipolar circuits such as a linear circuit or an ECL (Emitter Coupled Logic) may be easily formed on the same chip, thus realizing a multi-functional integrated circuit.
Various studies have been made to achieve higher operation speed of the I.sup.2 L. It has been recently pointed out that it is important to achieve a short storage time or a time required for a switching transistor to sink the minority carriers stored at an emitter or base region of a switching transistor of the next stage. This is described, for example, in IEEE Journal of Solid-State Circuits, Vol. SC-14. No. 2, April 1979, pp. 327 to 336. In order to eliminate storage of minority carriers, it is effective to optimize the concentration profile of the epitaxial semiconductor layer and the emitter region as well as to minimize the size of a region at which the minority carriers are stored. In view of this, it has been conventionally proposed to manufacture an I.sup.2 L by a method to be described in FIGS. 1(a) to 1(c). According to this conventional method, referring to FIGS. 1(a) to 1(c), an n.sup.+ -type buried layer 2 is selectively formed in a p-type silicon substrate 1. After growing an n-type epitaxial layer 3 on the substrate 1, a thick field oxide film 4 for element isolation is formed by selective oxidation. After selectively forming a silicon oxide film 5 on the prospective element forming region by the CVD process or photolithography, boron is thermally diffused using the silicon oxide film 5 as a mask to form a p.sup.+ -type base region 6 and a p.sup.+ -type injector 7 (FIG. 1(a)). In the next step, an arsenic-doped polycrystalline silicon film (arsenic is an n-type impurity) is deposited over the entire surface of the structure. The arsenic-doped polycrystalline silicon film is selectively etched to form polycrystalline silicon patterns 8a and 8b on collector region forming regions (FIG. 1(b)). Thermal oxidation under heating is performed to grow a thick thermal oxide film 9 around the polycrystalline patterns 8a and 8b and to grow a thin thermal oxide film 10 on the p.sup.+ -type injector 7. Arsenic doped in the polycrystalline silicon patterns 8a and 8b is diffused into the p.sup.+ -type base region 6 to form n.sup.+ -type collector regions 11a and 11b. The thin thermal oxide film 10 is etched to provide the polycrystalline silicon patterns 8a and 8b as collector electrodes 12a and 12b. After an aluminum film is deposited over the entire surface of the structure, the aluminum film on the field oxide film 4 and the silicon oxide film 5 is patterned to form a base electrode 13 and an injector electrode 14. An integrated circuit including an I.sup.2 L is thus completed (FIG. 1(c)). Referring to FIGS. 1(a) to 1(c), reference numerals 15a to 15c denote base contact holes, and reference numeral 16 denotes an injector contact hole.
In the conventional method for manufacturing an integrated circuit with an I.sup.2 L described above, the base contact holes can be formed by self-alignment with respect to the collector electrodes 12a and 12b, so that the base electrode 13 may be able to contact with the base region 6 with a wider area. Moreover, the contact area of the base region 6 may be made smaller than the total area of the collector regions 11a and 11b. An I.sup.2 L thus manufactured is capable of high speed operation and the ratio of the collector area to the base area (SC/SB) is increased. Therefore, the current amplification factor (h.sub.FE) can be improved and higher integration can also be achieved. However, with an I.sup.2 L of the structure as described above, the p-n junction below the base contact holes 15a to 15c of the npn transistors becomes parasitic to the p-n junctions of the base and emitter immediately below the collector regions 11a and 11b, as shown in FIG. 1(c). A parasitic p-n junction degrades the ratio (SC/SB) of the npn transistor for the dc operation. Then, the current amplification factor and the fanout of the npn transistor are reduced. Furthermore, during the switching operation, the minority carriers are stored in the n-type epitaxial layer of the parasitic diode, resulting in an increase in the diffusion capacitance and degradation in the operating speed of the I.sup.2 L gate.
In order to prevent formation of a parasitic junction as described above, an I.sup.2 L of a structure is proposed wherein silicon oxide layers 17a to 17c are buried below the base contact holes 15a to 15c of the npn transistor as shown in FIG. 2. Another silicon oxide layer 17d is also buried below the injector contact hole 16. With the I.sup.2 L of this structure, the formation of a parasitic p-n junction can indeed be prevented. However, this structure simultaneously brings about defects to be described below in the manufacturing method therefor.
(1) The silicon oxide layers 17a to 17d are formed in the surface layer of the n.sup.+ -type buried layer 2. However, when the n-type epitaxial layer 3 is grown thereafter, the silicon oxide layers 17a to 17d and the surrounding semiconductor layer tend to be converted into polycrystalline silicon. This adversely affects the characteristics of the transistor formed in the vicinities of the silicon oxide layers 17a to 17d.
(2) Since the p.sup.+ -type base region 6 of the npn transistors must be in contact with the silicon oxide layers 17a to 17c, the thickness of the n-type epitaxial layer 3 is limited to the depth of the base region 6.
(3) Alignment of the silicon oxide layers 17a to 17c with the polycrystalline silicon patterns 8a and 8b as the diffusion sources for the collector regions 11a and 11b of the npn transistors requires the use of a mask. Thus, the silicon oxide layers 17a to 17c cannot be self-aligned with the collector regions 11a and 11b, resulting in lower integration.
Due to these defects, the conventional method for burying the silicon oxide layers and for forming the epitaxial layer thereon to form an I.sup.2 L gate is subject to structural and performance problems.
As a method for forming an intrinsic npn transistor with the silicon oxide layers for preventing formation of a parasitic p-n junction, it is possible to grow an intrinsic transistor forming region by the selective epitaxial growth method. However, at the current stage, the selective epitaxial growth method is not necessarily suitable for mass production.